68精品久久久久久欧美,最近中文字幕完整在线看一,久久亚洲男人天堂,最近中文字幕完整视频高清1

#include "N76E003.h"
#include "SFR_Macro.h"
#include "Function_define.h"
#include "Common.h"
#include "Delay.h"

//========================================================================
//  The test process:
//    1. Power on is run as default HIRC, show LED Fsys tickle faster
//     2. toggle P3.0 to GND.
//    2. call modify Fsys code to LIRC.
//    3. LED tickle speed slowly than before.
//========================================================================
void main(void)
{

/* Note
  MCU power on system clock is HIRC (16 MHz)
    Please keep P3.0 HIGH before you want to modify Fsys to LIRC
*/
    
      Set_All_GPIO_Quasi_Mode;                       // In Common.h define
    set_CLOEN;                                                                // Also can check P1.1 CLO pin for clock to find the Fsys change.
        set_P30;
        while (P30)                                                                    // when P3.0 keep high, clock out HIRC
        {   
                clr_GPIO1;                                                            // Check LED output tickle time
        Timer0_Delay1ms(200);
        set_GPIO1;
        Timer0_Delay1ms(200);
        }
    
////------------------------------------------------------------------------------------------------------
///*********************************** Change system closk source ***************************************/
////------------------------------------------------------------------------------------------------------
              
////***** HIRC enable part *****               
//        set_HIRCEN;                                                //step1: enable HIRC clock source run
//        while((CKSWT&SET_BIT5)==0);                //step2: check ready
//        clr_OSC1;                                                    //step3: switching system clock source if needed
//        clr_OSC0;
//        while((CKEN&SET_BIT0)==1);                //step4: check system clock switching OK or NG
//
////***** LIRC enable part*****
////** Since LIRC is always enable, switch to LIRC directly
        set_OSC1;                                                    //step3: switching system clock source if needed
        clr_OSC0;  
        while((CKEN&SET_BIT0)==1);                //step4: check system clock switching OK or NG     
        clr_HIRCEN;
   
////--------------------------------------------------------------------------------------------------------
    
/*
  Now Fsys = LIRC , LED tickle slowly.
*/
    while(1)
    {
                clr_GPIO1;                                                            // Check LED output tickle time
        clr_P00;
        set_GPIO1;
        set_P00;
    }
/* =================== */
}

#define set_P30     P30      = 1
#define clr_P30     P30      = 0

////***** HIRC enable part *****               
//        set_HIRCEN;                                                //step1: enable HIRC clock source run
//        while((CKSWT&SET_BIT5)==0);                //step2: check ready
//        clr_OSC1;                                                    //step3: switching system clock source if needed
//        clr_OSC0;
//        while((CKEN&SET_BIT0)==1);                //step4: check system clock switching OK or NG
//
////***** LIRC enable part*****
////** Since LIRC is always enable, switch to LIRC directly
        set_OSC1;                                                    //step3: switching system clock source if needed
        clr_OSC0;  
        while((CKEN&SET_BIT0)==1);                //step4: check system clock switching OK or NG     
        clr_HIRCEN;

#define set_HIRCST  BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT|=SET_BIT5;EA=BIT_TMP;
#define set_LIRCST  BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT|=SET_BIT4;EA=BIT_TMP;
#define set_ECLKST  BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT|=SET_BIT3;EA=BIT_TMP;
#define set_OSC1    BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT|=SET_BIT2;EA=BIT_TMP;
#define set_OSC0    BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT|=SET_BIT1;EA=BIT_TMP;

#define clr_HIRCST  BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT&=~SET_BIT5;EA=BIT_TMP;
#define clr_LIRCST  BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT&=~SET_BIT4;EA=BIT_TMP;
#define clr_ECLKST  BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT&=~SET_BIT3;EA=BIT_TMP;
#define clr_OSC1    BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT&=~SET_BIT2;EA=BIT_TMP;
#define clr_OSC0    BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT&=~SET_BIT1;EA=BIT_TMP;