leahkinn LPDDR3 178ball
作者： 來(lái)源: 發(fā)布時(shí)間：2020-06-02 瀏覽：15
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| 關(guān)鍵字： leahkinn LPDDR3 178ball |
| leahkinn LPDDR3 178ballLTFP0006ES3-ZJn1LTFP0066ES3-ZJn1LTFP0666ES3-ZJn1LTFP6666ES3-ZJn11GB/2GB/3GB/4GB Mobile-LPDDR3Product Features• Ultra-low-voltage core and I/O power supplies•Data rate–1866 Mb/s/pin• 8n prefetch DDR architecture• 8 internal banks for concurrent operation• Multiplexed, double data rate, command/address inputs; commands entered on each CK_t/CK_cedge• Bidirectional/differential data strobe per byte of data (DQS_t/DQS_c)• Programmable READ and WRITE latencies (RL/WL)• Burst length: 8• Per-bank refresh for concurrent operation• Auto temperature-compensated self refresh (ATCSR) by built-in temperature sensor• Partial-array self refresh (PASR)• Deep power-down mode (DPD)• Selectable output drive strength (DS)• Clock-stop capability• Lead-free (RoHS-compliant) and halogen-free packagingOptions•VDD1/VDD2/VDDCA/VDDQ:1.8V/1.2V/1.2V/1.2V• Array configuration– 256 Meg x 32 (SDP)– 512 Meg x 32 (DDP)– 768 Meg x 32 (TDP)– 1024 Meg x 32 (QDP)• Packaging– 12.5mm x 11.5mm, 178-ball FBGA package• Operating temperature range– From –30°C to +85°CLTFP0006ES3-ZJn1LTFP0066ES3-ZJn1LTFP0666ES3-ZJn1LTFP6666ES3-ZJn1 |
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編輯：admin 最后修改時(shí)間：2020-06-02
